The integrity of a Flip-Chip Package (FCPBGA) assembly depends directly on the adhesive quality of the interface formed between chip-level passivation polyimide coating and the underfill material that is used to fill interstitial gaps between solder bumps in the cavity between the packaging plastic laminate and the chip. The integrity of a wirebond assembly similarly depends on the adhesion between the passivation and encapsulant materials. Historically, chips having die sizes in excess of about 150 mm2 experience sufficiently high chip edge coefficient of thermal expansion (CTE) forces during thermal cycling that this interface is prone to failure if it is not of adequate integrity. Failure initiates at high DNP (distance to neutral point) locations, such as a corner. Once the interface begins to come apart, this delamination can spread over large areas of the chip corner, and can even propagate as a crack down into the BEOL levels of the chip. Deep thermal cycle and accelerated temperature cycling stress testing of parts is used to force failure of any interface with substandard reliability, during the normal technology and product evaluation phase. Chip parts with die sizes approaching 20 mm per edge and above (400 mm2+) are particularly sensitive to this failure mechanism and require very careful engineering of this critical interface for long-term survival of the part. One technique is to add adhesion-enhancing design features near the chip edge, but this may consume chip area that could be used for circuitry or pose constraints on die size. The integrity of underfill to passivation adhesion in the package is currently a critical problem in the industry. Needed are additional ways to improve the durability and integrity of the passivation to encapsulant bond.